The present invention relates to a digital signal processor. More particularly, it relates to techniques which are especially effective for use in a digital signal processor having a multiply-and-add function necessary for digital filter realization.
Digital signal processors having a multiply-and-add function necessary for so-called filter processing for the realization of a digital filter are well known. The digital signal processors adopt a stored program system employing microprograms and include therein an instruction ROM (read only memory) for storing microinstructions, and a data ROM as well as a data RAM (random access memory) for storing processing and other data.
A digital signal processor having the multiply-and-add function is described in "Users' Manual of Hitachi Digital Signal Processor (HSP) HD61810" issued in September 1985 by Hitachi, Ltd.
FIG. 10 shows a partial block diagram of the digital signal processor described in the above literature. In addition, FIG. 11 is an example of a processing flow diagram in the case where a transversal type digital filter is equivalently realized in the digital signal processor of FIG. 10.
Referring to FIGS. 10 and 11, sampling data items X.sub.1 -X.sub.n, which are formed in such a way that an input analog signal is sampled at a predetermined period and then digitized, are temporarily stored in the corresponding addresses of a data RAM represented by symbol DRAM. The sampling data items are read out of the DRAM successively as sampling data items X.sub.i, and they are input to a multiplier unit MULT together with filter coefficients C.sub.i which are read out of the corresponding addresses of a data ROM represented by symbol DROM. The results (products) of the multiplier unit MULT are further input to an arithmetic logic unit ALU, in which they are added with the output signals of accumulators ACCA and ACCB which contain the last added result (sum) of the arithmetic logic unit ALU.
The sampling data items X.sub.i read out of the DRAM are held for one machine cycle by a delay register DREG comprising two stages of latches. The held data items X.sub.i are input to the addresses A.sub.i+1 of the DRAM after the read operation of the next sampling data items X.sub.i+1. Consequently, the sampling data items X.sub.1 -X.sub.n are, in effect, delayed for one sampling period and are successively shifted within the DRAM.
In this manner, the sampling data items X.sub.i and the filter coefficients C.sub.i are successively input to the MULT, and the sampling data items X.sub.i are successively shifted within the DRAM, whereby the following multiply-and-add processing necessary for digital filter implementation as illustrated in FIG. 11 is executed: ##EQU1## thus realizing the equivalent digital filter.
Limitations exist in the digital signal processor referred to above. DRAM is constructed of a single-port RAM, the sampling data items X.sub.i held in the delay register DREG are written into the addresses A.sub.i+1 of the DRAM after the read operation of the next sampling data items X.sub.i+1 has ended. Because of this, the read operation and the write operation must be performed in a time-division fashion within one memory cycle of the DRAM, so that the potential levels of each data line and each sense amplifier in the DRAM change twice within one memory cycle. This leads to the problem that the overall access time required increases as the DRAM size increases. The result thus places a limit on the shortening of the machine cycle of the digital signal processor.